UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1600

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1598
(5) External interrupt falling, rising edge specification registers 5 (INTF5, INTR5)
Notes 1. To read or write bits 8 to 15 of the INTF5 and INTR5 registers in 8-bit or 1-bit units, specify them as
Remark
The INTF5 and INTR5 registers are 16-bit or 8-bit registers in which bits 0 to 6 and 9 are used to specify
detection of the falling and rising edges of the external interrupt pins (INTP07 to INTP11 and INTP23 to
INTP25).
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 0000H/00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
Caution Be sure to set the INTF5n and INTR5n bits to 00 if the corresponding pin is not used as the
Remark
2. V850ES/JJ3-E only
INTR5 (INTR5H
INTF5 (INTF5H
INTF5n
bits 0 to 7 of the INTF5H and INTR5H registers.
For the valid edge specification combinations, see Table 25-9.
0
0
1
1
port function, an edge may be detected. Therefore, set the INTF5n and INTR5n bits to 00, and
then set the port mode.
INTP07 to INTP11 and INTP23 to INTP25 pins.
n = 0 to 6: Control of the INTP07 to INTP11, INTP23, and INTP24 pins
n = 9: Control of the INTP25 pin
(INTR5L)
(INTF5L)
After reset: 0000H
After reset: 0000H
Note 1
Note 1
CHAPTER 25 INTERRUPT/EXCEPTION PROCESSING FUNCTION
)
)
INTR5n
0
1
0
1
15
15
0
7
0
0
7
0
Table 25-9. Valid Edge Specification
INTP24
INTR56
INTP24
INTF56
No edge detected
Rising edge
Falling edge
Both rising and falling edges
14
14
R/W
R/W
0
6
0
6
User’s Manual U19601EJ2V0UD
Note 2
Note 2
Note 2
Note 2
INTF55
INTP23
INTR55
INTP23
Address: INTF5 FFFFFC0AH,
Address: INTR5 FFFFFC2AH,
13
13
0
5
0
5
Note 2
Note 2
Note 2
Note 2
Valid Edge Specification (n = 0 to 6, 9)
INTF54
INTP11
INTR5L FFFFFC2AH, INTR5H FFFFFC2BH
INTR54
INTP11
INTF5L FFFFFC0AH, INTF5H FFFFFC0BH
12
12
0
4
0
4
INTP10
INTR53
INTP10
INTF53
11
11
0
3
0
3
INTF52
INTR52
INTP9
INTP9
10
10
0
2
0
2
INTF59
INTP25
INTR59
INTP25
INTR51
INTF51
INTP8
INTP8
9
1
9
1
Note 2
Note 2
Note 2
Note 2
INTF50
INTR50
INTP7
INTP7
8
0
0
8
0
0