UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1458

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1456
0
(13) RXFINF3: Reception status 3 register
Bit
This register indicates the status of the receive FIFO while reception is stopped.
Access
Address
Default value 0000 0001H. This register is cleared to its default value by all types of resets.
Cautions 1. Before rewriting a mode register related to reception or flow control, be sure to confirm
RXSTOP
31
23
15
Name
R
R
R
R
0
0
0
7
0
2. Be sure to set bits 31 to 1 to “0”.
that the RXFINF3.RXSTOP bit is set to 1.
This register is read-only, in 32-bit units.
002E 024CH
This bit is set to 1 if no data is in the receive FIFO while reception is stopped (by setting
MFFCONT.RXEN to 0).
Before rewriting a mode setting register related to reception or flow control, confirm that the
RXSTOP bit is set to 1.
0: Receive FIFO is operating.
1: Receive FIFO is not operating.
30
22
14
R
R
R
R
0
0
0
6
0
CHAPTER 23 ETHERNET CONTROLLER
29
21
13
R
R
R
R
0
0
0
5
0
User’s Manual U19601EJ2V0UD
28
20
12
R
R
R
R
0
0
0
4
0
27
19
11
R
R
R
R
0
0
0
3
0
Description
26
18
10
R
R
R
R
0
0
0
2
0
25
17
R
R
R
R
0
0
9
0
1
0
RXSTOP
24
16
R
R
R
R
0
0
8
0
0