UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 556

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

later detected, the count value of the 16-bit counter is stored in the TT0CCRn register, the 16-bit counter is cleared to
0000H, and a capture interrupt request signal (INTTT0CCn) is generated.
interrupt request signal (INTTT0OV) is generated at the next count clock, and the counter is cleared to 0000H and
continues counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Clear the overflow flag to 0
by executing the CLR instruction via software.
554
When the TT0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIT0n pin is
The pulse width is calculated as follows.
If the valid edge is not input to the TIT0n pin even when the 16-bit counter counted up to FFFFH, an overflow
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Remark
Pulse width = Captured value × Count clock cycle
Pulse width = (10000H × TT0OVF bit set (1) count + Captured value) × Count clock cycle
INTTT0CCn signal
TT0CCRn register
Remark
INTTT0OV signal
n = 0, 1
TIT0n pin input
16-bit counter
TT0OVF bit
TT0CE bit
FFFFH
0000H
n = 0, 1
Figure 9-40. Basic Timing in Pulse Width Measurement Mode
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
0000H
User’s Manual U19601EJ2V0UD
D
0
D
1
Cleared to 0 by
CLR instruction
D
2
D
3