UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1371

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

002E 0000H
002E 0004H
002E 0008H
002E 000CH
002E 0010H
002E 0014H
002E 0054H
002E 0058H
002E 005CH
002E 0064H
002E 0080H
002E 0094H
002E 0098H
002E 009CH
002E 00A0H
002E 00A4H
002E 00C8H
002E 00CCH
002E 00D0H
002E 00DCH
002E 00E0H
002E 0130H
002E 0134H
002E 0140H
002E 0144H
002E 0148H
002E 014CH
0002E 150H
002E 0154H
002E 0158H
002E 015CH
002E 0160H
002E 0164H
002E 0168H
002E 016CH
002E 0170H
002E 0174H
002E 0178H
002E 017CH
Offset Address
(3) Register list
MACC1
MACC2
IPGT
IPGR
CLRT
LMAX
LSA1
LSA2
PTVR
VLTP
MIIC
MCMD
MADR
MWTD
MRDD
MIND
AFR
HT1
HT2
CAR1
CAR2
CAM1
CAM2
RBYT
RPKT
RFCS
RMCA
RBCA
RXCF
RXPF
RXUO
RALN
RFLR
RCDE
RFCR
RUND
ROVR
RFRG
RJBR
Symbol
MAC setting register 1
MAC setting register 2
Back-to-back IPG register
Non back-to-back IPG register
Collision register
Maximum packet length register
Station address register 1
Station address register 2
Pause timer value read register
VLAN type register
MII configuration register
MII command register
MII address register
MII write data register
MII read data register
MII indicator register
Address filter register
Hash table register 1
Hash table register 2
Carry register 1
Carry register 2
Carry mask register 1
Carry mask register 2
Reception byte counter
Reception packet counter
Reception FCS error frame counter
Reception multicast packet counter
Reception broadcast packet counter
Reception control frame packet counter
Reception pause frame packet counter
Reception undefined control packet counter
Reception alignment error counter
Reception frame length error counter
Reception code error counter
Reception false carrier counter
Reception undersize packet counter
Reception oversize packet counter
Reception fragment counter
Reception jabber counter
CHAPTER 23 ETHERNET CONTROLLER
Table 23-2. Register List (MAC) (1/2)
User’s Manual U19601EJ2V0UD
Register Name
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Manipulation
8
Unit
16
32
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
00000000H
00000000H
00000013H
00000E13H
0000380FH
00000600H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
00000000H
Default Value
1369