UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1509

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note These bits are not used during transmission. Set these bit to 0.
Remark
26
25 to 16
15 to 0
Bit
The Size field is 16 bits. Setting 0 to this field is prohibited. If 0 is set, an error interrupt is generated. If
FFFFH is set to this field, transfer of 64K – 1 bytes is executed.
O
Status
Size
Note
Name
Note
This bit indicates occurrence of an overflow error during reception.
The CPU clears this bit when it creates or obtains buffer data (a descriptor). If an overflow error
occurs during reception, the Ethernet controller writes back 1 to the control bit 0 of the first
descriptor of the packet, and sets control bit E of the descriptor in which the overflow error
occurred. No interrupt is generated.
This field indicates status information during reception. If control bit S is 1, the value of the
Status field is valid. The CPU clears this bit when it creates or obtains buffer data (a descriptor).
During DMA transfer of a receive packet, the Ethernet controller writes a valid value to the
Status field of the first descriptor of the current packet and sets control bit S to 1 each time
transfer of one packet has been completed,.
The bits in the status field are shown below. The value of the reception status monitor
(RXSTMON1) is written to these bits.
This field indicates the size (in bytes) of the buffer data indicated by this descriptor. During
DMA transfer of a receive packet, the Ethernet controller writes the length of one transferred
packet to the Size field of the last descriptor of the current packet each time transfer of one
packet has been completed.
0: No overflow
1: Overflow
16
17
18
19
20
21
23 to 25
Table 23-10. Buffer Descriptor Format (2/2)
CHAPTER 23 ETHERNET CONTROLLER
Bit
User’s Manual U19601EJ2V0UD
CEPS
RCV
RCRCF
RLOR
DBNB
RXOK
FTYP[0:2]
Description
Name
000:RBRO
001:RMUL
010:USOP
011:VLAN
100:RPCF
101:RCFR
110:”Nomal”
111:”Reserved”
1507