UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 769

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) Transmission interrupt request signal
(a) Transmission enable interrupt request signal (INTUBnTIT)
(b) FIFO transmission end interrupt request signal (INTUBnTIF)
If the data to be transmitted next has not been written to the transmit data register, the transmit operation is
suspended.
Caution In the single mode, the transmission enable interrupt request signal (INTUBnTIT) occurs
Remark
• In single mode (UBnFIC0.UBnMOD bit = 0)
• In FIFO mode (UBnFIC0.UBnMOD bit = 1)
• If pending mode is specified (UBnFIC0.UBnITM bit = 0) in FIFO mode
• If pointer mode is specified (UBnFIC0.UBnITM bit = 1) in FIFO mode
The FIFO transmission end interrupt request signal (INTUBnTIF) occurs when no more data is in transmit
FIFO and the transmit shift register in the FIFO mode (UBnFIC0.UBnMOD bit = 1). After the INTUBnTIF
signal has occurred, clear the pending INTUBnTIT signal in the pending mode (UBnFIC0.UBnITM bit = 0)
by clearing the FIFO (UBnFIC0.UBnTFC bit = 1). If the INTUBnTIF signal occurs because writing the
next transmit data to transmit FIFO is delayed (if all transmit data have not been transmitted), do not
clear the FIFO.
In the single mode, the transmission enable interrupt request signal (INTUBnTIT) occurs when transmit
data can be written to the UBnTX register (when 1 byte of data is transferred from the UBnTX register
to the transmit shift register).
In the FIFO mode, the INTUBnTIT signal occurs when transmit data of the number set as the trigger
specified by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits is transferred from transmit FIFO to the
transmit shift register (if transmit data of the number set as the trigger can be written).
If the pending mode is specified in the FIFO mode, the second INTUBnTIT signal is held pending after
the first INTUBnTIT signal has occurred, until as many transmit data as the number set as the trigger
by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits are written to transmit FIFO, even if the generation
condition of the second INTUBnTIT signal is satisfied. When as many transmit data as the number set
as the trigger are written to transmit FIFO in response to the first INTUBnTIT signal, the second
pending INTUBnTIT signal is generated.
If the pointer mode is specified in the FIFO mode, the second INTUBnTIT signal occurs when the
generation condition of the second INTUBnTIT signal is satisfied even if as many transmit data as the
number set as the trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits are not written to transmit
FIFO when the first INTUBnTIT signal occurs.
when the UBnTX register becomes empty (when 1 byte of data is transferred from the
UBnTX register to the transmit shift register). In the FIFO mode, the FIFO transmission end
interrupt request signal (INTUBnTIF) occurs when data is no longer in transmit FIFO and the
transmit shift register (when the FIFO and register are empty). However, the INTUBnTIT
signal or INTUBnTIF signal is not generated if the transmit data register becomes empty
due to RESET input.
n = 0, 1
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
User’s Manual U19601EJ2V0UD
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