UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 754

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

752
Note After receive FIFO (UBnRXAP) is cleared (UBnRFC bit = 1), accessing the registers related to UARTBn
Remark
is prohibited for the duration of four cycles of f
confirmed by reading the UBnFIC0 register. If these registers are accessed, the operation is not
guaranteed.
f
XX
: Peripheral clock
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
UBnRFC
UBnIRM
UBnITM
In the FIFO mode, the INTUBnTIR signal is generated as soon as receive data of
the number set as the trigger by the UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits
have been transferred from the receive shift register to receive FIFO. After the
INTUBnTIR signal request has been generated, specify the timing of actually
generating the INTUBnTIR signal as the pending mode or pointer mode. For
details, see 16.6 (2) Pending mode/pointer mode.
•
•
•
In the FIFO mode, the INTUBnTIT signal is generated as soon as transmit data of
the number set as the trigger by the UBnFIC2.UBnTT3 to UBnFIC2.UBnTT0 bits
have been transferred from transmit FIFO to the transmit shift register. After the
INTUBnTIT signal request has been generated, specify the timing of actually
generating the INTUBnTIT signal as the pending mode or pointer mode. For details,
see 16.6 (2) Pending mode/pointer mode.
The UBnRFC bit is valid only in the FIFO mode (UBnMOD bit = 1), and is invalid
in the single mode (UBnMOD bit = 0).
When 1 is written to the UBnRFC bit, the pointer to receive FIFO is cleared to 0.
In the pending mode (UBnIRM bit = 0), the interrupt request signal (INTUBnTIR)
held pending is cleared
register (URIC) is not cleared to 0. Clear this bit to 0 as necessary.
When 0 is written to the UBnRFC bit, the status is retained. No operation, such
as clearing or setting, is executed.
When writing 1 to the UBnRFC bit, be sure to clear the UBnCTL0.UBnRXE bit to
0 (disabling reception). If 1 is written to the UBnRFC bit when the UBnRXE bit is
1 (reception enabled), the operation is not guaranteed.
0
1
0
1
0
1
Normal status
Clear (This bit automatically returns to 0 after receive FIFO is cleared.)
Pending mode
Pointer mode
Pending mode
Pointer mode
Specification of INTUBnTIR interrupt generation timing in FIFO mode
Specification of INTUBnTIT interrupt generation timing in FIFO mode
Note
Receive FIFO (UBnRXAP) clear trigger bit
User’s Manual U19601EJ2V0UD
. However, bit 7 (URIF) of the interrupt control
XX
or until clearing the UBnRFC bit (automatic recovery) is
(2/2)