UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1616

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1614
Item
Main clock oscillator (f
Subclock oscillator (f
Internal oscillator (f
PLL
CPU
DMA controller
Interrupt controller
Timer
Real-time counter (RTC)
Watchdog timer (WDT2)
Serial interface
A/D converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
Internal data
CAN
USB function
Ethernet controller
Notes 1. To realize low power consumption, stop the A/D converter, USB function, and Ethernet controller before
Note 2
2.
shifting to the IDLE1 mode.
μ
PD70F3783, 70F3786 only
Setting of IDLE1 Mode
TAA0 to TAA5
TAB0, TAB1
TMM0 to TMM3
TMT0
CSIFn
CSIE0, CSIE1
I
UARTCx
UARTB0, UARTB1
R
2
C0m
)
XT
X
)
)
Table 27-5. Operating Status in IDLE1 Mode
Oscillation enabled
Oscillation enabled
Operable
Stops operation
Stops operation
Stops operation (but standby mode release is possible)
Stops operation
Stops operation
Operable when f
count clock
Stops operation
Operable when f
selected as the count clock
Operable when f
count clock
Operable when the SCKFn input clock is selected as the count clock
(n = 0 to 4: V850ES/JH3-E, n = 0 to 6: V850ES/JJ3-E)
Operable when the SCKE0 or SCKE1 input clock is selected as the count clock
Stops operation (m = 0 to 3: V850ES/JH3-E, m = 0 to 4: V850ES/JJ3-E)
Stops operation (but UARTC0 is operable when the ASCKC0 input clock is selected)
(x = 0 to 5: V850ES/JH3-E, x = 0 to 7: V850ES/JJ3-E)
Stops operation
Holds operation (conversion result held)
Stops operation (output held)
Operable
Stops operation
See CHAPTER 5 BUS CONTROL FUNCTION.
Retains status before IDLE1 mode was set
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the IDLE1 mode was set.
Stops operation
Operable when the UCLK input clock is selected as the count clock or the PLL is
operating
Stops operation
CHAPTER 27 STANDBY FUNCTION
User’s Manual U19601EJ2V0UD
When Subclock Is Not Used
Note 1
Note 1
R
X
R
/8 is selected as the
(divided BRG) is
is selected as the
−
Operating Status
Note 1
Oscillation enabled
Operable when f
the count clock
Operable
Operable when f
the count clock
When Subclock Is Used
R
R
/8 or f
or f
XT
XT
is selected as
is selected as