UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1378

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1376
14 to 8
6 to 0
(4) IPGR: Non back-to-back IPG register
Caution Be sure to set bits 31 to 15 and 7 to “0”.
Bit
Access
Address
Default value 0000 0E13H. This register is cleared to its default value by all types of resets.
IPGR1
IPGR2
31
23
15
Name
R
R
R
R
0
0
0
7
0
This register can be read and written in 32-bit units.
002E 000CH
Carrier sense period
These bits set the carrier sense period of the first half of the IPG in transmission other than back-to-
back transmission. The calculation expression used to calculate the carrier sense period is as
follows.
• Carrier sense period = (2 + IPGR1) x time required to transmit 4 bits
Set the carrier sense period to 2/3IPG to satisfy the specification of IEEE802.3 (refer to 23.5.2 (5)
Inter-packet gap (IPG)).
IPG in transmission other than back-to-back transmission
These bits set the IPG in transmission other than back-to-back transmission. The expression used
to calculate the IPG is as follows.
• IPG = (5 + IPGR2) x time required to transmit 4 bits
The carrier sense period set by IPGR1 is included in the IPG set by IPGR2. Set the IPG to the time
required to transmit at least 96 bits to satisfy the specification of IEEE802.3 (refer to 23.5.2 (5)
Inter-packet gap (IPG)).
R/W
R/W
30
22
14
R
R
0
0
6
CHAPTER 23 ETHERNET CONTROLLER
R/W
R/W
29
21
13
R
R
0
0
5
User’s Manual U19601EJ2V0UD
R/W
R/W
28
20
12
R
R
0
0
4
IPGR1
IPGR2
R/W
R/W
27
19
11
R
R
0
0
3
Description
R/W
R/W
26
18
10
R
R
0
0
2
R/W
R/W
25
17
R
R
0
0
9
1
R/W
R/W
24
16
R
R
0
0
8
0