UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 952

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

950
(7) Interrupt request signal generator
(8) Serial clock controller
(9) Serial clock wait controller
(10) ACK generator, stop condition detector, start condition detector, and ACK detector
(11) Data hold time correction circuit
(12) Start condition generator
(13) Stop condition generator
(14) Bus status detector
This circuit controls the generation of interrupt request signals (INTIICn).
An I
• The falling edge of the eighth or ninth clock of the serial clock (set by IICCn.WTIMn bit)
• Interrupt occurrence due to stop condition detection (set by IICCn.SPIEn bit)
In master mode, this circuit generates the clock output via the SCL0n pin from the sampling clock (n = 0 to 2).
This circuit controls the wait timing.
Remark
These circuits are used to generate and detect various statuses.
This circuit generates the hold time for the data corresponding to the falling edge of the SCL0n pin.
This circuit generates a start condition when the IICCn.STTn bit is set.
However, when in the communication reservation disabled status (IICFn.IICRSVn bit = 1) and when the bus is
not released (IICFn.IICBSYn bit = 1), this request is ignored and the IICFn.STCFn bit is set to 1.
This circuit generates a stop condition when the IICCn.SPTn bit is set.
This circuit detects whether the bus is released by detecting a start condition and stop condition.
However, the bus status cannot be detected immediately after operation, so set the bus status detector to the
initial status by using the IICFn.STCENn bit.
2
C interrupt is generated by either of the following two triggers.
n = 0 to 3 (V850ES/JH3-E)
n = 0 to 4 (V850ES/JJ3-E)
User’s Manual U19601EJ2V0UD
CHAPTER 20 I
2
C BUS