UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1281

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(10) UF0 bulk-in 2 register (UF0BI2)
UF0BI2
Bit position
7 to 0
The UF0BI2 register is a 64-byte × 2 FIFO that stores data for Endpoint3. This register consists of two banks
of 64-byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE
and CPU sides. The toggle operation takes place when no data is in the FIFO on the SIE side (counter value
= 0) and when the FIFO on the CPU side is correctly written (FIFO full or BKI2DED bit = 1).
This register is write-only, in 8-bit units. When this register is read, 00H is read.
The hardware transmits data to the USB bus in synchronization with the IN token for Endpoint3 only when the
BKI2NK bit of the UF0EN register is set to 1 (when NAK is not transmitted). The address at which data is to
be written or read is managed by the hardware. Therefore, FW can transmit data to the host only by writing
the data to the UF0BI2 register sequentially. A short packet is transmitted when data is written to the UF0BI2
register and the BKI2DED bit of the UF0DEND register is set to 1 (BKIN2 bit of UF0EPS0 register = 1 (data
exists)). A Null packet is transmitted when the UF0BI2 register is cleared and the BKI2DED bit of the
UF0DEND register is set to 1 (BKIN2 bit of the UF0EPS0 register = 1 (data exists)). When the data is
transmitted correctly, a FIFO toggle operation occurs. The BKI2DT bit of the UF0IS2 register is set to 1, and
an interrupt request is generated for the CPU. An interrupt request or DMA request can be selected by using
the DQBI2MS bit of the UF0IDR register.
The operation of the UF0BI2 register is illustrated below.
BKI27
7
BKI27 to
BKI20
Bit name
BKI26
6
CHAPTER 22 USB FUNCTION CONTROLLER (USBF)
BKI25
These bits store data for Endpoint3.
5
BKI24
4
User’s Manual U19601EJ2V0UD
BKI23
3
BKI22
2
Function
BKI21
1
BKI20
0
00200112H
Address
After reset
Undefined
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