UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1726

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(T
Remarks 1. T = 1/f
Bus Hold (CLKOUT Asynchronous)
1724
HLDRQ high-level width
HLDAK low-level width
Delay time from HLDAK↑ to bus output t
Delay time from HLDRQ↓ to HLDAK↓
Delay time from HLDRQ↑ to HLDAK↑
Delay time from bus float to HLDAK↓
A
(2) During bus hold
= −40 to +85°C, V
Note.
(a) CLKOUT asynchronous
Address bus (output)
2. n: Number of wait clocks inserted in the bus cycle
3. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
WR0, WR1 (output)
CLKOUT (output)
HLDAK (output)
Parameter
The sampling timing changes when a programmable wait is inserted.
CS0, CS2,
CS3 (output)
HLDRQ (input)
ASTB (output)
Data bus (I/O)
V850ES/JJ3-E only, V850ES/JH3-E is CS0, CS2
RD (output),
CPU
DD
(f
Note
= EV
CPU
: CPU operating clock frequency)
DD
= UV
CHAPTER 35 ELECTRICAL SPECIFICATIONS
DD
t
t
t
t
t
WHQH
WHAL
DHAC
DHQHA1
DHQHA2
DFHA
= AV
Symbol
REF0
User’s Manual U19601EJ2V0UD
<44>
<45>
<46>
<47>
<48>
<49>
, V
SS
<47>
Conditions
= AV
TI
SS
<49>
= 0 V, C
TH
L
0.5T + 17
= 50 pF)
T + 16
T − 10
MIN.
2.5T
−7
0
TH
<45>
Hi-Z
Hi-Z
Hi-Z
Hi-Z
TH
<48>
<44>
1.5T + 31
MAX.
TI
<46>
Unit
ns
ns
ns
ns
ns
ns