UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 876

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

874
(10) Continuous mode
The continuous mode is set when the CEnCTL0.CEnTMS bit is 1 (n = 0, 1).
In this mode, transfer is started when the CEnTXE bit or CEnRXE bit is 1 and when data is in the CSIBUFn
register (CEnSTR.CEnEMF register). At this time, set the number of transfer data in advance by using the
CEnCTL3.CEnSFN3 to CEnCTL3.CEnSFN0 bits. If data exceeding the number of transfer data specified by
the CEnCTL3.CEnSFN3 to CEnCTL3.CEnSFN0 bits are written to the CSIBUFn register, the excess data are
ignored and not transferred.
If no data is in the CSIBUFn register (CEnEMF bit = 1), transfer is kept waiting until transmit data or dummy
data is written to the CEnTX0 register.
If data is written to the CEnTX0 register when transmission or reception is enabled (CEnTXE or CEnRXE bit
is 1), the CEnSTR.CEnTSF bit (transfer status flag) is set to 1 and the transfer data indicated by the SIOn
load/store CSIBUFn pointer is loaded from the CSIBUFn register to SIOn register. Then transfer processing
is started.
When transfer processing of one data is completed in the reception mode or transmission/reception mode,
the received data is overwritten from the SIOn register to the transfer data in the CSIBUFn register indicated
by the SIOn load/store CSIBUFn pointer, and then the pointer is incremented. By consecutively reading the
transfer data from the CEnRX0 register after all data in the CSIBUFn register have been transferred (when
the INTCEnT interrupt has occurred), the receive data can be sequentially read while the read CSIBUFn
pointer is incremented. If read operation is executed for the data number exceeding the received data count
from the CEnRX0 register, however, the read value is undefined.
In the transmission mode, the SIOn load/store CSIBUFn pointer is incremented when transfer processing of
one data has been completed.
In all modes (transmission, reception, and transmission/reception modes), when data has been transferred by
the value set by the CEnCTL3.CEnSFN3 to CEnCTL3.CEnSFN0 bits, the CEnTSF bit is cleared to 0 and the
transmission/reception completion interrupt (INTCEnT) is output.
To transfer the next data, be sure to write 1 to the CEnSTR.CEnPCT bit and clear all the CSIBUFn pointers to
0.
The “number of transferred data (SIOn load/store CSIBUFn pointer value)” can always be read from the
CEnSTR.CEnSFP3 to CEnSTR.CEnSFP0 bits.
Caution The CEnSTR register is in the same status when transfer data is written (before start of
transfer) after the CSIBUFn pointer is cleared (CEnSTR.CEnPCT bit = 1) and when 16 data
have been transferred (CEnSTR.CEnSTR.CEnFLF bit = 0, CEnSTR.CEnEMF bit = 1,
CEnSTR.CEnSFP3 to CEnSTR.CEnSFP0 bits = 0000).
CHAPTER 18 CLOCKED SERIAL INTERFACE E WITH FIFO (CSIE)
User’s Manual U19601EJ2V0UD