UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 936

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

934
SIFn pin capture
INTCFnR signal
(2) Operation timing
CFnSCE bit
CFnTSF bit
SCKFn pin
SIFn pin
(1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A3H to the CFnCTL0 register, and select the reception mode, MSB first, and continuous transfer
(4) The CFnSTR.CFnTSF bit is set to 1 by performing a dummy read of the CFnRX register, and the
(5) When a serial clock is input, capture the receive data of the SIFn pin in synchronization with the serial
(6) When reception is completed, the reception completion interrupt request signal (INTCFnR) is
(7) When a serial clock is input in the CFnCTL0.CFnSCE bit = 1 status, continuous reception is started.
(8) To end continuous reception with the current reception, write the CFnSCE bit = 0.
(9) Read the CFnRX register.
(10) When reception is completed, the INTCFnR signal is generated, and reading of the CFnRX register is
(11) Read the CFnRX register.
(12) If an overrun error occurs, write CFnSTR.CFnOVE bit = 0, and clear the error flag.
(13) To release the reception enable status, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnRXE bit =
Remark
timing
external clock (SCKFn), and slave mode.
mode at the same time as enabling the operation of the communication clock (f
device waits for a serial clock input.
clock.
generated, and reading of the CFnRX register is enabled.
enabled. When CFnSCE bit = 0 is set before communication completion, clear the CFnTSF bit to 0 to
end the receive operation.
0 after checking that the CFnTSF bit = 0.
(1)
(2)
(3)
n = 0 to 4 (V850ES/JH3-E)
n = 0 to 6 (V850ES/JJ3-E)
(4)
(5)
Bit 7
Bit 6
CHAPTER 19 CLOCKED SERIAL INTERFACE F (CSIF)
Bit 5
Bit 4 Bit 3
User’s Manual U19601EJ2V0UD
Bit 2
Bit 1
(6) (7) (8) (9)
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
(10)
Bit 0
CCLK
).
(11) (13)
CCLK
) =