UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1268

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1266
(4) UF0 EP0 write register (UF0E0W)
UF0E0W
Bit position
The UF0E0W register is a 64-byte FIFO that stores the IN data (passes it to SIE) sent to the host in the data
stage to Endpoint0.
This register is write-only, in 8-bit units. When this register is read, 00H is read.
The hardware transmits data to the USB bus in synchronization with an IN token only when the EP0NKW bit of
the UF0E0N register is set to 1 (when NAK is not transmitted). When data is transmitted and when the host
correctly receives the data, the EP0NKW bit of the UF0E0N register is automatically cleared to 0 by hardware.
A short packet is transmitted when data is written to the UF0E0W register and the E0DED bit of the UF0DEND
register is set to 1 (EP0W bit of the UF0EPS0 register = 1 (data exists)). A Null packet is transmitted when the
UF0E0W register is cleared and the E0DED bit of the UF0DEND register is set to 1 (EP0W bit of the UF0EPS0
register = 1 (data exists)).
The UF0E0W register is cleared to 0 when the next SETUP token is received while transmission has not been
completed yet. If the stage of control transfer (read) changes to the status stage while ACK has not been
correctly received in the data stage, the UF0E0W register is automatically cleared to 0. At the same time, it is
also cleared to 0 if the EP0NKW bit of the UF0E0N register is 1.
If the UF0E0W register is read while no data is in it, 00H is read.
The operation of the UF0E0W register is illustrated below.
7 to 0
E0W7
7
E0W7 to
E0W0
Bit name
E0W6
6
CHAPTER 22 USB FUNCTION CONTROLLER (USBF)
E0W5
These bits store the IN data sent to the host in the data stage to Endpoint0.
5
E0W4
4
User’s Manual U19601EJ2V0UD
E0W3
3
E0W2
2
Function
E0W1
1
E0W0
0
00200106H
Address
After reset
Undefined