UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 21

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 24 DMA FUNCTION (DMA CONTROLLER) ..................................................................1528
CHAPTER 25 INTERRUPT/EXCEPTION PROCESSING FUNCTION .............................................1553
23.7 Receive Checksum ...............................................................................................................1525
23.8 Notes ........................................................................................................................................1527
24.1 Features .................................................................................................................................1528
24.2 Configuration ........................................................................................................................1529
24.3 Registers................................................................................................................................1530
24.4 Transfer Targets....................................................................................................................1539
24.5 Transfer Modes .....................................................................................................................1539
24.6 Transfer Types ......................................................................................................................1540
24.7 DMA Channel Priorities ........................................................................................................1541
24.8 Time Related to DMA Transfer ............................................................................................1541
24.9 DMA Transfer Start Factors .................................................................................................1542
24.10 DMA Abort Factors ...............................................................................................................1543
24.11 End of DMA Transfer ............................................................................................................1543
24.12 Operation Timing ..................................................................................................................1543
24.13 Cautions.................................................................................................................................1548
25.1 Features .................................................................................................................................1553
25.2 Non-Maskable Interrupts......................................................................................................1565
25.3 Maskable Interrupts ..............................................................................................................1570
25.4 Software Exception...............................................................................................................1586
25.5 Exception Trap ......................................................................................................................1589
25.6 External Interrupt Request Input Pins (NMI and INTP00 to INTP25)................................1593
23.6.2
23.6.3
23.6.4
23.6.5
23.7.1
23.8.1
25.2.1
25.2.2
25.2.3
25.3.1
25.3.2
25.3.3
25.3.4
25.3.5
25.3.6
25.3.7
25.3.8
25.4.1
25.4.2
25.4.3
25.5.1
25.5.2
25.6.1
Descriptor mechanism............................................................................................................. 1505
Frame transmission................................................................................................................. 1514
Frame reception ...................................................................................................................... 1519
Error occurrence...................................................................................................................... 1524
Processing by software ........................................................................................................... 1525
Notes on FIFO......................................................................................................................... 1527
Operation ................................................................................................................................ 1567
Restore.................................................................................................................................... 1568
NP flag .................................................................................................................................... 1569
Operation ................................................................................................................................ 1570
Restore.................................................................................................................................... 1572
Priorities of maskable interrupts .............................................................................................. 1573
Interrupt control register (xxICn).............................................................................................. 1577
Interrupt mask registers 0 to 7 (IMR0 to IMR7) ....................................................................... 1582
In-service priority register (ISPR) ............................................................................................ 1584
ID flag...................................................................................................................................... 1585
Watchdog timer mode register 2 (WDTM2) ............................................................................. 1585
Operation ................................................................................................................................ 1586
Restore.................................................................................................................................... 1587
EP flag..................................................................................................................................... 1588
Illegal opcode .......................................................................................................................... 1589
Debug trap .............................................................................................................................. 1591
Noise elimination ..................................................................................................................... 1593
User’s Manual U19601EJ2V0UD
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