UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1233

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
Bit position
4, 0
n = 1, 2
m = 2 where n = 1
m = 4 where n = 2
BKOnDT
Bit name
CHAPTER 22 USB FUNCTION CONTROLLER (USBF)
These bits indicate that data has been correctly received in the UF0BOn register
(Endpoint m).
These bits are automatically set to 1 by hardware when data has been correctly received
and the FIFO has been toggled. At the same time, the corresponding bits of the
UF0EPS0 register are also set to 1. They are not set to 1 when the data is a Null packet.
These bits are automatically cleared to 0 by hardware when the value of the UF0BOnL
register becomes 0 as a result of reading the UF0BOn register by FW.
These bits are automatically cleared to 0 when all the contents of the FIFO on the CPU
side have been read. However, the interrupt request is not cleared if data is in the FIFO
on the SIE side at this time, and the INTUSBF1 signal does not become inactive. The
signal is kept active if data is successively received.
1: Reception has been completed correctly (interrupt request is generated).
0: Reception has not been completed (default value).
User’s Manual U19601EJ2V0UD
Function
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