UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1139

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.12 Interrupt Function
signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or
more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register. After
an interrupt source has occurred, the corresponding interrupt status bit must be cleared to 0 by software.
1
2
3
4
5
6
No.
The CAN module provides 6 different interrupt sources.
The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request
Notes 1. The C0MCTRL.IE bit (message buffer interrupt enable bit) of the corresponding message buffer has to
Remark m = 00 to 31
CINTS0
CINTS1
CINTS2
CINTS3
CINTS4
CINTS5
Name
Interrupt Status Bit
2. This interrupt is generated when the transmission/reception error counter is at the warning level, or in
3. This interrupt is generated when a stuff error, form error, ACK error, bit error, or CRC error occurs.
4. This interrupt is generated when the CAN module is woken up from the CAN sleep mode because a
Note 1
Note 1
be set to 1 for that message buffer to participate in the interrupt generation process.
the error passive or bus-off state.
falling edge is detected at the CAN reception pin (CAN bus transition from recessive to dominant).
C0INTS
C0INTS
C0INTS
C0INTS
C0INTS
C0INTS
Register
CIE0
CIE1
CIE2
CIE3
CIE4
CIE5
Table 21-20. List of CAN Module Interrupt Sources
Name
Interrupt Enable Bit
Note 1
Note 1
CHAPTER 21 CAN CONTROLLER
C0IE
C0IE
C0IE
C0IE
C0IE
C0IE
Register
User’s Manual U19601EJ2V0UD
Request Signal
INTC0TRX
INTC0REC
INTC0ERR
INTC0WUP
Interrupt
Message frame successfully transmitted from
message buffer m
Valid message frame reception in message buffer m
CAN module error state interrupt
CAN module protocol error interrupt
CAN module arbitration loss interrupt
CAN module wakeup interrupt from CAN sleep
mode
Note 4
Interrupt Source Description
Note 2
Note 3
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