UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1739

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(T
Notes 1. When the start condition is satisfied, the first clock pulse is generated after the hold time.
Remark n = 0 to 4
SCL0n clock frequency
Bus free time
(Between start and stop conditions)
Hold time
SCL0n clock low-level width
SCL0n clock high-level width
Setup time for start/restart conditions
Data hold
time
Data setup time
SDA0n and SCL0n signal rise time
SDA0n and SCL0n signal fall time
Stop condition setup time
Pulse width of spike suppressed by
input filter
Capacitive load of each bus line
A
(8) I
= −40 to +85°C, V
2. The system requires a minimum of 300 ns hold time internally for the SDA0n signal (at V
3. If the system does not extend the SCL0n signal low hold time (t
4. The high-speed mode I
5. Cb: Total capacitance of one bus line (unit: pF)
2
C bus mode
Note 1
signal) in order to occupy the undefined area at the falling edge of SCL0n.
(t
speed mode I
CBUS compatible master
I
2
C mode
HD
Parameter
:
• If the system does not extend the SCL0n signal low hold time:
• If the system extends the SCL0n signal low hold time:
DAT
t
Output the next data bit to the SDA0n line before the SCL0n line is released (t
+ 250 = 1,250 ns: Normal mode I
) needs to be satisfied.
SU:DAT
DD
= EV
≥ 250 ns
2
C bus so that it meets the following conditions.
DD
= UV
2
C bus can be used in a normal-mode I
CHAPTER 35 ELECTRICAL SPECIFICATIONS
f
t
t
t
t
t
t
t
t
t
t
t
Cb
DD
CLK
BUF
HD:STA
LOW
HIGH
SU:STA
HD:DAT
SU:DAT
R
F
SU:STO
SP
= AV
Symbol
<75>
<76>
<77>
<78>
<79>
<80>
<81>
<82>
<83>
<84>
<85>
REF0
User’s Manual U19601EJ2V0UD
, V
2
C bus specification).
SS
= AV
MIN.
0
250
4.7
4.0
4.7
4.0
4.7
5.0
4.0
Note 2
0
−
−
−
−
Normal Mode
SS
= 0 V)
MAX.
1000
100
300
400
−
−
−
−
−
−
−
−
−
−
2
C bus system. In this case, set the high-
LOW
20 + 0.1Cb
20 + 0.1Cb
), only the maximum data hold time
100
MIN.
0
1.3
0.6
1.3
0.6
0.6
0.6
High-Speed Mode
Note 2
0
−
0
−
Note 4
Note 5
Note 5
Rmax.
0.9
MAX.
400
300
300
400
IHmin.
50
−
−
−
−
−
−
−
−
Note 3
+ t
SU:DAT
of the SCL0n
= 1,000
Unit
kHz
pF
μ
μ
μ
μ
μ
μ
μ
ns
ns
ns
μ
ns
1737
s
s
s
s
s
s
s
s