UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 406

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOABnk pin. After the one-shot
pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is generated
again while the one-shot pulse is being output, it is ignored.
count value matches the value of the CCR0 buffer register.
(INTTABnCCk) is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register.
the trigger.
404
TABnCTL1
TABnCTL0
When the TABnCE bit is set to 1, TABn waits for a trigger. When the trigger is generated, the 16-bit counter is
The output delay period and active level width of the one-shot pulse can be calculated as follows.
The compare match interrupt request signal INTTABnCC0 is generated when the 16-bit counter counts up after its
The valid edge of the external trigger input or setting the software trigger (TABnCTL1.TABnEST bit) to 1 is used as
Remark
Output delay period = (Set value of TABnCCRk register) × Count clock cycle
Active level width = (Set value of TABnCCR0 register − Set value of TABnCCRk register + 1) × Count clock cycle
(a) TABn control register 0 (TABnCTL0)
(b) TABn control register 1 (TABnCTL1)
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1.
Remark
TABnSYE
k = 1 to 3,
n = 0, 1
TABnCE
Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (1/3)
0/1
0
n = 0, 1
TABnEST
0/1
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
TABnEEE
0/1
0
User’s Manual U19601EJ2V0UD
0
0
0
0
TABnMD2 TABnMD1 TABnMD0
TABnCKS2 TABnCKS1 TABnCKS0
0/1
0
The compare match interrupt request signal
0/1
1
0/1
1
0, 1, 1:
One-shot pulse output mode
Generate software trigger
when 1 is written
0: Operate on count clock
1: Count by external event
Select count clock
0: Stop counting
1: Enable counting
selected by TABnCKS0 to
TABnCKS2 bits
count input signal
Note