UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1375

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9
8
7
6
5
3
2
1
0
Bit
SRXEN
PARF
PUREP
FLCHT
NOBO
CRCEN
PADEN
FULLD
HUGEN
Name
Control packet pass
Pure preamble
Length field check
No backoff
CRC appending
PAD appending
Full-duplex enable
Huge packet enable
Reception enable
0: Reception is disabled.
1: The function of the reception data interface is enabled. If the setting of this bit is changed while
0: A control frame is judged as a control frame.
1: No received packet, including a control frame, is judged as a control frame. The value of the
0: The data of a preamble is not checked.
1: A reception status interrupt is generated if an illegal preamble is detected.
0: The length field is not checked.
1: The value of the length field and data field is checked, and a status interrupt is generated.
0: Packets are transmitted by using the backoff algorithm.
1: Packets are always transmitted without using the backoff algorithm.
0: CRC is not appended.
1: CRC is automatically appended to the end of a packet.
0: PAD is not appended.
1: PAD is appended to packet if its length is less than 64 bytes. At this time, CRC is automatically
0: Half-duplex operation
1: Full-duplex operation
0: Transmission/reception of a packet that exceeds the value of the maximum packet length
1: Transmission/reception of a packet that exceeds the value of the maximum packet length
the CRS signal is asserted, the new setting becomes valid after the CRS signal has been
deasserted, regardless of the setting of the FULLD bit.
pause timer is not updated even if a valid pause control frame is received, regardless of the
setting of the RXFC bit.
The end of a transmission packet must be a valid FCS. The MAC checks the FCS. If the FCS
value is not correct, the MAC reports an error by using the transmission status interrupt
(TXSTATUS).
An internally generated frame check sequence (FCS) is appended to the end of a transmission
packet.
appended to the end of the packet regardless of the setting of the CRCEN bit.
register (LMAX) is stopped.
register (LMAX) is not stopped.
CHAPTER 23 ETHERNET CONTROLLER
User’s Manual U19601EJ2V0UD
Description
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