UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1545
UPD70F3786GJ-GAE-AX
Manufacturer Part Number
UPD70F3786GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3786GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Company:
Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
UPD70F3786GJ-GAE-AX
Manufacturer:
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24.10 DMA Abort Factors
memory/on-chip peripheral I/O.
24.11 End of DMA Transfer
bit is cleared to 0 and TCn bit is set to 1, a DMA transfer end interrupt request signal (INTDMAn) is generated for the
interrupt controller (INTC) (n = 0 to 3).
confirm completion of DMA transfer by using the DMA transfer end interrupt or polling the TCn bit.
24.12 Operation Timing
DMA transfer is aborted if a bus hold occurs.
The same applies if transfer is executed between the internal memory/on-chip peripheral I/O and internal
When the bus hold is cleared, DMA transfer is resumed.
When DMA transfer has been completed the number of times set to the DBCn register and when the DCHCn.Enn
The V850ES/JH3-E and V850ES/JJ3-E do not output a terminal count signal to external devices. Therefore,
Figures 24-1 to 24-4 show DMA operation timing.
CHAPTER 24 DMA FUNCTION (DMA CONTROLLER)
User’s Manual U19601EJ2V0UD
1543
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