UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1575

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

25.3.3 Priorities of maskable interrupts
being serviced. Multiple interrupts can be controlled by priority levels.
programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt
control register (xxICn). When two or more interrupts having the same priority level specified by the xxPRn bit are
generated at the same time, interrupt request signals are serviced in order depending on the priority level allocated to
each interrupt request type (default priority level) beforehand. For more information, see Table 25-2 and Table 25-3.
The programmable priority control customizes interrupt request signals into eight levels by setting the priority level
specification flag.
when multiple interrupts are to be used, clear the ID flag to 0 beforehand (for example, by placing the EI instruction in
the interrupt service program) to set the interrupt enable mode.
The INTC performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is
There are two types of priority level control: control based on the default priority levels, and control based on the
Note that when an interrupt request signal is acknowledged, the PSW.ID flag is automatically set to 1. Therefore,
Remark xx: Identification name of each peripheral unit (see Table 25-4 Interrupt Control Register (xxICn))
n: Peripheral unit number (see Table 25-4 Interrupt Control Register (xxICn)).
CHAPTER 25 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User’s Manual U19601EJ2V0UD
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