UPD70F3786GJ-GAE-AX Renesas Electronics America, UPD70F3786GJ-GAE-AX Datasheet - Page 1365

• Manufacturer Part Number: UPD70F3786GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3786GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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23.1
a FIFO controller for flow control, and a checksum calculation unit (only for received packets) conforming to RFC1071.
23.1.1 Functions
The Ethernet controller includes a 10/100 Mbps Ethernet Media Access Controller (MAC) conforming to IEEE802.3,
(1) MAC
(2) FIFO
(3) DMAC in Ethernet controller
(4) Checksum calculation
General
• 10/100 Mbps full-duplex communication, half-duplex communication, and flow control conforming to
• MII supported as physical layer device (PHY) interface
• Accessing PHY registers via serial management interface supported
• Statistics counter to support RMON/SNMP (RFC2665, RFC2819)
• Packet filtering based on address types
• VLAN frame detection
• Transmit/receive FIFO size: Transmit FIFO = 2 KB, receive FIFO = 2 KB
• FIFO status register
• Interrupts generated by transmission/reception status and FIFO status
• Data transfer (DMA)
• Reception status DMA transfer
• Reading (in pointer chain format), analyzing, and writing back buffer descriptors
• Controlling interrupts in packet transfers
• Receive checksum calculation conforming to RFC1071
The MAC header and FCS of a received packet are automatically identified and the checksum, excluding the
IEEE802.3 (1998 Edition) supported
dummy header, for verifying the received packet is generated.
CHAPTER 23 ETHERNET CONTROLLER
User’s Manual U19601EJ2V0UD
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