BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 948

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LCLCP clock period (nT)
LCLCP high level pulse width
(including phase reversal)
LCLCP low level pulse width
(including phase reversal)
Data valid to LCLCP fall
(including phase reversal)
LCLCP fall to data hold
(including phase reversal)
4.3.6
AC measurement conditions
• CL = 20 pF
Note: The letter “n” in the equations represents the value set in LCDTiming2<PCD_HI><PCD_LO> plus two. The following
Parameter
Note: The “Equation” column in the table shows the specifications under the conditions DVCC3LCD = 1.8 to 3.6 V
LCD Controller
AC measurement conditions
• The letter “T” used in the equations in the table represents the period of internal bus frequency (f
• Output level: High = 0.7 × DVCC3LCD, Low = 0.3 × DVCC3LCD
limitations apply to the “n” value depending on operating frequency.
which is one-half of the CPU clock (f
and DVCC1A = DVCC1B = DVCC1C = 1.4 to 1.6 V.
Example 1: When f
Example 2: When f
LD0 to LD23
LCLCP
Symbol
HCLK
HCLK
t
t
t
t
t
CWH
CWL
DSU
DHD
CW
= 48 MHz, LCDTiming2<PCD_HI><PCD_LO> ≥ 0 (n ≥ 2).
= 100 MHz, LCDTiming2<PCD_HI><PCD_LO> ≥1 (n ≥ 3).
((n＋1)T / 2) – 6.0
t
t
t
CWH
CWH
((n-1)T / 2) – 5.0
((n-1)T / 2) – 6.0
((n＋1)T / 2) – 5
DSU
TMPA900CM- 947
TENTATIVE
When n = even
When n = even
When n = even
When n = even
LD0 to LD23 out
When n = odd
When n = odd
When n = odd
When n = odd
(nT / 2) – 5.0
(nT / 2) – 6.0
(nT / 2) – 6.0
(nT / 2) – 5
Min
FCLK
30
t
CW
).
t
t
t
CWL
CWL
DHD
Equation
Max
LCDTiming2<IPC> = 1
LCDTiming2<IPC> = 0
100 MHz
(n=3)
30.0
15.0
14.0
5.0
4.0
96 MHz
(n=3)
31.25
15.8
14.8
5.4
4.4
TMPA900CM
2009-10-14
48MHz
(n=2)
41.6
15.8
15.8
14.8
14.8
HCLK
),
Unit
ns