BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 617

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(2)
• T0: Reset start
• T1: Reset recognition (more than 2.5 µs after T0)
• T2: Device Chirp-K complete (more than 1.0 ms after T1)
• T3: FS operation start (1.0 ms to 2.5 ms after T2)
• T4: Reset end (more than 10 ms after T0)
(UDC2-Output)
xcvr_select
(UDC2-Output)
term_select
(UDC2-Output)
When Operating in FS Mode after Reset
usb_reset
DP/DM
When UDC2 detects SE0 for more than approximately 68 μs after T0, it recognizes the
reset from the host and drives usb_reset “H”. At the same time, UTMI starts the device
Chirp-K operation.
When the host supports FS mode, the host chirp-KJ operation is not performed. If no host
Chirp-KJ is detected in approximately 2 ms after T2, UDC2 initiates FS mode. At this
point, usb_reset is driven “L”. The period in which usb_reset remains “H” is
approximately 3.5 ms.
When SE0 from the host finishes and the device enters an idle state, it indicates the end of
reset operation. The reset period from the host lasts a minimum of 10 ms.
Upon recognizing SE0 from the host, UDC2 starts counting to recognize the reset.
UDC2 completes the device Chirp-K operation approximately 1.5 ms after T1.
time
Figure 3.16.28 Reset operation timing (FS mode after Chirp)
J
(H)
T0
SE0
T1
TENTATIVE
TMPA900CM- 616
Device
Chirp-K
T2
T3
SE0
TMPA900CM
2009-10-14
T4
J