BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 252
BMSKTOPASA900(DCE)
Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Specifications of BMSKTOPASA900(DCE)
Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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[31:24]
[23:16]
[15:13]
[12]
[11]
[10]
[9:7]
[6]
[5:3]
[2]
[1:0]
Bit
Note: These registers cannot be read while they are in the Reset state.
6.
Reserved
Reserved
burst_align
bls
Reserved
−
wr_bl
wr_sync
rd_bl
rd_sync
mw
smc_opmode0_0_3 (SMC Opmode Registers 0<0>)
Symbol
Bit
RO
RO
RO
RO
RO
−
RO
RO
RO
RO
RO
Type
TENTATIVE
TMPA900CM- 251
0x20
0xE0
0y000
0y0
0y1
Undefined
0y000
0y0
0y000
0y0
0y10
Reset
Value
Read as 0x20.
Read as 0xE0. Specify whether or not the address [31:24]
can be compared
Memory burst boundary split set value:
0y000 = bursts can cross any address boundary
0y001 = split at the 32-beat burst boundary
0y010 = split at the 64-beat burst boundary
0y011 = split at the 128-beat burst boundary
0y100 = split at the 256-beat burst boundary
other = Reserved
bls timing :
0y0 = chip select
0y1 = Reserved
−
Read as undefined.
Write memory burst length:
0y000 = 1-beat
0y001 = 4-beats
other = Reserved
Memory operation mode:
0y0 = asynchronous write operation
0y1 = Reserved.
Read memory burst length:
0y000 = 1 beat
0y001 = 4 beats
other = Reserved
Memory operation mode:
0y0 = asynchronous read operation
0y1 = Reserved.
Memory data bus width :
0y00 = Reserved
0y01 = 16-bits
0y10 = 32-bits
0y11 = Reserved
Address = (0xF430_1000) + (0x0104)
Description
TMPA900CM
2009-10-14
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