BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 500

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

[31:30]
[29]
[28:26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
Bit
−
mw_rerror_en
−
dmac_reg_rd_en
udc2_reg_rd_en
mr_ahberr_en
mr_ep_dset_en
mr_end_add_en
mw_ahberr_en
mw_timeout_en
mw_end_add_en
mw_set_add_en
Note: For the operation of interrupt signals, refer to “3.16.2.7 Interrupt Signal (INTS[21])”.
2. UDINTENB (Interrupt Enable register)
Symbol
source of the interrupt signal (INTS[21] output signal) can be disabled. Writing 1 will
enable the corresponding interrupt source.
enabled or disabled status of each bit, an interrupt may occur at the same time as this
register was enabled. If such behavior should be avoided, the corresponding bit of
Interrupt Status register should be cleared in advance.
register is bits [15:8] of the INT register of UDC2, not this register. See the section of
UDC2.
By writing 0 into the corresponding bit of this register, the corresponding interrupt
Since the corresponding bit of Interrupt Status register will be set regardless of the
The interrupt control register corresponding to bits [7:0] of the Interrupt Status
Bit
−
R/W
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
TENTATIVE
TMPA900CM- 499
Undefined
0y0, (-)
Undefined
0y0, (-)
0y0, (-)
0y0, (-)
0y0, (-)
0y0, (-)
0y0, (-)
0y0, (-)
0y0, (-)
0y0, (-)
Reset
Value
Read as undefined. Write as zero.
Master Write endpoint read error
0y0: Disable
0y1: Enable
Read as undefined. Write as zero.
DMAC register read complete
0y0: Disable
0y1: Enable
UDC2 register read access complete
0y0: Disable
0y1: Enable
Master Read transfer error status interrupt enable
0y0: Disable
0y1: Enable
Master Read endpoint data set status interrupt enable
0y0: Disable
0y1: Enable
Master Read transfer end status interrupt enable
0y0: Disable
0y1: Enable
Master Write transfer error status interrupt enable
0y0: Disable
0y1: Enable
Master Write transfer timeout status interrupt enable
0y0: Disable
0y1: Enable
Master Write transfer end status interrupt enable
0y0: Disable
0y1: Enable
Master Write transfer address request status interrupt
enable
0y0: Disable
0y1: Enable
Address = (0xF440_0000) + (0x0004)
Description
TMPA900CM
2009-10-14