BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 258

Manufacturer Part Number

BMSKTOPASA900(DCE)

KIT STARTER TMPA900 USB JTAG

Manufacturer

Evaluation Board, Cable(s), Software and Documentation

For Use With/related Products

TMPA900CMXBG

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

(b) Clock Variety

2. Bus matrix 2 of LCDDA and USB handles the earliest bus request first. If

1. Dynamic memory clock: Use HCLK clock

2. Static memory clock: Use HCLK or 1/2 HCLK

multiple bus requests are accepted simultaneously, they are handled according

to hardware priority.

Hardware priority is shown following

LCDDA (high) C1 → USB (low)

Control clock is controlled in PLLCG circuit:

LCDDAbus request

USB bus request

Handling priority : ① → ② → ③ →④

A dotted line is the point of handling end, where bus is released.

TMPA900CM- 257