BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 541

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UDTOUTCNT
eprx_dataset
UDMWTOUT
mw_enable
(5) Timeout
should stagnate before reaching the Master Write End Address during the transfer. In
order to cope with such circumstances, you can set the timeout function.
point of timeout will be transferred to AHB.
with the timeout function enabled, but the counter will be reset to the preset value
when the OUT transfer from the USB host to the relevant endpoint is received and
begin recounting (see the figure below). It means that the time until timeout is "from
the point when the last transfer from the USB host to the relevant endpoint has
occurred during the Master Write transfer to the preset time,” rather than "from the
point when the Master Write transfer has begun to the preset time.”
Write Timeout register to “Disable 0” before starting the Master Write transfer. In that
case, the transfer will not finish until reaching the preset Master Write End Address.
Master Write transfers would not finish if the OUT transfer from the USB host
When this timeout function is used, all data stored in the buffer in UDC2AB at the
Timeout can be processed with the following operation:
1. Make an access to the Master Write Timeout register before starting a Master
2. Start the Master Write transfer in accordance with the instruction in the
3. When the timeout has occurred, the int_mw_timeout interrupt will be asserted.
4. In Master Write Current Address register, the address to which the transfer has
Please note that the timeout counter advances during the Master Write transfer
If you do not use the timeout function, be sure to set the timeout_en bit of Master
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Write transfer and set timeoutset (timeout time) to make timeout_en enabled 1.
preceding section.
(The int_mw_end_add interrupt will not be asserted.) In that case, the Master
Write transfer is not completed to reach the Master Write End Address. UDC2AB
clears the mw_enable bit of DMAC Setting register to 0.
completed to the AHB end can be confirmed.
Figure 3.16.11 Example of MW timeout count
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OUT Transfer
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TENTATIVE
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