BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 201
BMSKTOPASA900(DCE)
Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Specifications of BMSKTOPASA900(DCE)
Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 201 of 959
- Download datasheet (5Mb)
f
HCLK
CLKCR5< SEL_SMC_MCLK >
MPMC0 or MPMC1 depending on SDRAM to use.
The following shows differences in supported memory between MPMC0 and MPMC1. Select
Refer to chapters on respective circuits for details.
The following shows the MPMC block diagram.
MPMC0:
MPMC1:
Note 1: SDR SDRAM and DDR SDRAM cannot be used concurrently.
Note 2: The two memory controllers cannot be used by dynamically switching between them. The memory controller
÷2
to be used must be fixed.
Mode setting pin
SELMEMC
32-bit/16-bit Standard type SDR SDRAM
32-bit/16-bit Mobile type SDR SDRAM
32-bit/16-bit NOR Flash (Asynchronous, Separate bus only)
32-bit/16-bit SRAM (Asynchronous, Separate bus only)
16-bit LVCMOS type DDR SDRAM
32-bit/16-bit NOR Flash (Asynchronous, Separate bus only)
32-bit/16-bit SRAM (Asynchronous, Separate bus only)
0
1
Standard/Mobile type SDR
Static Memory Controller
Static Memory Controller
LVCMOS type DDR
SDRAM Controller
SDRAM Controller
TENTATIVE
TMPA900CM- 200
MPMC0
MPMC1
MPMC
SMC
SMC
DMC
DMC
Operation mode
Use MPMC0
Use MPMC1
SELMEMC
SELMEMC
External Bus Interface
EBI
TMPA900CM
2009-10-14
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