BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 465

Manufacturer Part Number

BMSKTOPASA900(DCE)

KIT STARTER TMPA900 USB JTAG

Manufacturer

Evaluation Board, Cable(s), Software and Documentation

For Use With/related Products

TMPA900CMXBG

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

In this configuration, during idle periods:

FIFO, SP0FSS is driven Low and transmission is started.

further half SP0CLK period later, the SP0CLK master clock pin goes High.

later after the last bit has been latched. For continuous transfers, SP0FSS must be

pulsed High between each data transfer.

SPI (continuous transfer, <SPO> = 0 & <SPH> = 0)

• SP0CLK is forced Low

• SP0FSS is forced High

• the transmit data line SP0DO is undefined.

One half SP0CLK clock later, valid data is transferred to the SP0DO pin. One

For single transfers, SP0FSS is returned to High (idle state) one SP0CLK period

When the SSP is configured as the master and there is valid data in the transmit

TMPA900CM- 464