BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 598

KIT STARTER TMPA900 USB JTAG

BMSKTOPASA900(DCE)

Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Datasheets

Specifications of BMSKTOPASA900(DCE)

Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data flow on
USB cable
Register access
EP0_DATASET
INT_STATUS
INT_SETUP
INT_EP0
UDC2
Host
Note: Figure 3.16.21 shows the flow in High-Speed transfers. In Full-Speed transfers, the "PING" packet shown in
1.
2.
3.
(3) Control-WR transfer (with DATA-Stage)
Figure 3.16.21 Flow of control in Control-WR transfers (with DATA-Stage)
the figure is not issued. Also, the "NYET" packet is replaced by the "ACK" packet.
To be processed in the same way as in the SETUP-Stage described in (1).
When the data is received from the host with no problem, UDC2 asserts the
EP0_DATASET flag and asserts the INT_EP0 flag. When this flag is asserted, read the
data from EP0_FIFO after confirming the received data size in the EP0_Datasize
register, or read the data from EP0_FIFO polling the EP0_DATASET flag.
When the byte size of received data has been read, UDC2 deasserts the EP0_DATASET
flag.
To be processed in the same way as in the STATUS-Stage described in (1).
SETUP-Stage
DATA-Stage
STATUS-Stage
SETUP
The flow of control in Control-WR transfer (with DATA-Stage) is shown below.
SETUP-Stage
INT-Reg.
(8 bytes)
DATA0
Read
ACK
INT-Reg.
Write
Register Read (8 bytes)
Setup-Data storage
OUT
(Received data)
DATA1
Issue Setup_Received
Command
NAK
PING
TENTATIVE
TMPA900CM- 597
ACK
OUT
INT-Reg.
(Received data)
Read
DATA1
DATA-Stage (OUT)
INT-Reg.
NYET
Write
EP0_FIFO Read
PING
ACK
OUT
INT-Reg.
Read
(Received data)
DATA0/1
INT-Reg.
Write
NYET
EP0_FIFO Read
Issue Setup_Fin
Command
TMPA900CM
STATUS-Stage
IN
2009-10-14
INT-Reg.
DATA1
(0 byte)
Read
ACK
INT-Reg.
Write

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