BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 877
BMSKTOPASA900(DCE)
Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Specifications of BMSKTOPASA900(DCE)
Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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HcRevision
HcControl
HcCommandStatus
HcInterruptStatus
HcInterruptEnable
HcInterruptDisable
HcHCCA
HcPeriodCurrentED
HcControlHeadED
HcControlCurrentED
HcBulkHeadED
HcBulkCurrentED
HcDoneHead
HcFmInterval
HcFmRemaining
HcFmNumber
HcPeriodStart
HcLSThreshold
HcRhDescriptorA
HcRhDescripterB
HcRhStatus
HcRhPortStatus
-
-
HcBCR0
3.27.6
Note 1: The addresses listed in Table 3.27.1 are those mapped on the CPU registers.
Note 2: The Open HCI Specification Release 1.0a specifies the FrameRemaining (FR) and FrameRemainingToggle
Register
(OHCI) which are mapped into the memory space. The bus bridge logic for connecting with the
CPU also includes control registers.
Name
The USBHC contains a set of control registers compliant with the Open HCI Specification
These registers are directly accessible from the CPU via a 32-bit bus.
Registers
(FRT) bits in the HcFmRemaining register and the FrameNumber (FN) bit in the HcFmNumber register as
read-only to the Host Control Driver (HCD). However, the USB 1.1 OHCI Host Control Core allows write
accesses to these registers by HCD for debug purposes. If HCD writes to these registers, undefined results will
be obtained. These bits must not be written by HCD.
Table 3.27.1
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
0x0048
0x004C
0x0050
0x0054
0x0058
0x005C
0x0080
Address
(base+)
Registers Compliant with the USB Open HCI Specification
TENTATIVE
TMPA900CM- 876
Description
Base Address= 0xF450_0000
TMPA900CM
2009-10-14
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