BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 503

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

[31:1]
[0]
Bit
[Description]
timeoutset
timeout_en
a. <timeoutset>
b. <timeouten>
3.
The setting should not be changed during the Master Write transfer. Timeout occurs when
the number of times CLK_U was set is counted after the data of Master Write (Rx)
endpoint is exhausted.
The timeout counter comprises 32 bits of which upper 31 bits can be set by timeoutset
[31:1] of this register, while the lowest bit of the counter is set to 1.
As CLK_U is 30 MHz, approximately 33 [ns] to 143 [s] can be set as a timeout value.
While PHY is being suspended (CLK_U stopped), no timeout interrupt will occur as the
counter does not work.
Used to enable Master Write timeout. It is set to Enable by default.
The setting should not be changed during the Master Write transfer.
0y0: Disable
0y1: Enable
Symbol
Bit
This register is provided for controlling timeout during the Master Write operation.
UDMWTOUT (Master Write Timeout register)
R/W
R/W
Type
TENTATIVE
0x7FFFFFFF
0y1
TMPA900CM- 502
Reset
Value
Master Write timeout timer setting register
Master Write timeout enable register
0y0: Disable
0y1: Enable
Address = (0xF440_0000) + (0x0008)
Description
TMPA900CM
2009-10-14