BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 443

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.14.6.3 Serial Clock
I2CxCL signal
Note: The t
the low level period must be 5/Tprsck [s] or longer for externally input serial clocks,
regardless of the I2C0CR1<SCK> setting.
when a stop condition is generated are defined as t
defined as t
(1) Clock source
master mode.
I2C0CR1<SCK> is used to set the high and low periods of the serial clock to be output in
In master mode, the hold time when a start condition is generated and the setup time
When I2C0CR2<PIN> is set to 1 in slave mode, the time to the release of I2C0CL is
In both master and slave modes, the high level period must be 4/Tprsck [s] or longer and
t
t
fscl = 1/(t
HIGH
LOW
combination of bus load capacitance and pull-up resistor. If the clock synchronization function for
synchronizing clocks from multiple clocks is used, the actual clock period may differ from the specified setting.
= (j/Tprsck)
= (i/Tprsck)
HIGH
t
t
HIGH
LOW
HIGH
LOW
period may differ from the specified value if the rising edge becomes blunt depending on the
> = (5/Tprsck)
> = (4/Tprsck)
+ t
[s].
LOW
0y000
0y001
0y010
0y011
0y100
0y101
0y110
0y111
SCK
t
HIGH
)
Figure 3.14.12 I2CxCL output
Figure 3.14.13 SCLK input
t
HIGH
t
TENTATIVE
LOW
t
TMPA900CM- 442
HIGH
(i / Tprsck)
134
262
10
14
22
38
70
8
i
1/fscl
t
LOW
t
LOW
(j / Tprsck)
138
266
HIGH
12
14
18
26
42
74
j
[s].
TMPA900CM
2009-10-14