BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 101
BMSKTOPASA900(DCE)
Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Specifications of BMSKTOPASA900(DCE)
Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 101 of 959
- Download datasheet (5Mb)
3.8
3.8.1
The DMA controller has the following features:
DMAC (DMA Controller)
Number of channels
DMA start
Bus master
Priority
FIFO
Bus width
Burst size
transfer count
Address
Endian
Transfer type
Interrupt
Special function
Functional Overview
Item
8 ch
Hardware request
Software request
32 bits × 2 (AHB)
DMA channel 0 (high) to DMA channel 7
(low)
4 words × 8 ch
8/16/32 bits
1/4/8/16/32/64/128/256
~4095
Source address
Destination
address
Only little endian is supported.
Peripheral circuit (register) to pheripheral
circuit (register)
Peripheral circuit (register) to memory
Memory to peripheral circuit (register)
Memory to memory
Transfer end interrupt
Transfer error interrupt
Scatter/gather function
Table 3.8.1 DMA controller functions
TENTATIVE
TMPA900CM- 100
Function
incr / no-incr
incr / no-incr
16 types of DMA requests for
peripheral IPs. Refer to Table 3.8.2.
Activated by writing values into
DMACSoftBReq
DMA1, DMA2
Hardware-fixed
Source and destination can be
programmed separately.
Address wrapping is not supported.
DMA cannot start by hardware
request in memory to memory
transfer. Refer to the description of
DMACCxConfiguration register for
details.
Description
TMPA900CM
2009-10-14
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