BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 505

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

[31:9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Bit
−
m_burst_type
−
mr_reset
mr_abort
mr_enable
−
mw_reset
mw_abort
mw_enable
[Description]
a. <m_burst_type>
5. UDMSTSET (DMAC Setting register)
Symbol
Selects the type of HBURST[2:0] when making a burst transfer in Master Write/Read
transfers. The type of burst transfer made by UDC2AB is INCR8 (burst of 8 beat
increment type). Accordingly, 0 (initial value) should be set in normal situation. However,
in case INCR can only be used as the type of burst transfer based on the AHB specification
of the system, set 1 to this bit. In that case, UDC2AB will make INCR transfer of 8 beat.
Please note the number of beat in burst transfers cannot be changed.
Setting of this bit should be made in the initial setting of UDC2AB. The setting should not
be changed after the Master Write/Read transfers started.
Note: UDC2AB does not make burst transfers only in Master Write/Read transfers. It combines burst transfers and
0y0: INCR8
0y1: INCR
Bit
This register controls transfers of the built-in DMAC.
single transfers. This bit affects the execution of burst transfers only.
−
R/W
−
R/W1S
WO
−
R/W1S
R/W1S
WO
R/W1S
Type
Undefined
0y0, (-)
Undefined
0y0
0y0
0y0
Undefined
0y0
0y0
0y0
TENTATIVE
TMPA900CM- 504
Reset
Value
Read as undefined. Write as zero.
Master burst type
0y0: INCR8 (HBURST＝5h)
0y1: INCR (HBURST＝1h)
Read as undefined. Write as zero.
Master Read reset
0y0: No operation
0y1: Reset
Master Read abort
0y0: No operation
0y1: Abort
Master Read enable
0y0: Disable
0y1: Enable
Read as undefined. Write as zero.
Master Write reset
0y0: No operation
0y1: Reset
Master Write abort
0y0: No operation
0y1: Abort
Master Write enable
0y0: Disable
0y1: Enable
Address = (0xF440_0000) + (0x0010)
Description
TMPA900CM
2009-10-14