BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 643
BMSKTOPASA900(DCE)
Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Specifications of BMSKTOPASA900(DCE)
Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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I2STSLVON = 0x0
FIFO 1 set
WS cycle × 2 process
Transmission circuit State machine
[31:1]
[0]
[Description]
Bit
a. <I2STx_SLAVE>
3.
When this bit is set (0→ 1), the internal status (I2STST<I2STxSTATUS>) changes as
follows:
In the ACT state, the data stored in the FIFO is output.
When this bit is cleared (1 → 0), the internal status (I2STST<I2STxSTATUS>) changes as
follows:
In the SBY state, no data is output from the FIFO even when it contains data.
PRE_SBY
I2STSLVON (Tx I
−
I2STx_SLAVE
Bit Symbol
SBY (standby) → PRE_ACT → ACT
ACT → PRE_SBY → SBY
2
S Slave Control Register)
State that can read
FIFO of Transmission
circuit
−
R/W
Type
TENTATIVE
TMPA900CM- 642
SBY
ACT
Undefined
0y0
Reset
Value
Observe I2STSLVON = 0x1
WS edge
PRE_ACT
Read as undefined. Write as zero.
Transmit output enable
0y0: OFF
0y1: ON (FIFO read enabled)
WS cycle × 2 process
Address = (0xF204_0000) + (0x0004)
Description
TMPA900CM
2009-10-14
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