BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 240
BMSKTOPASA900(DCE)
Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Specifications of BMSKTOPASA900(DCE)
Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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AHB
Domain
APB slave
SMC I/F
I/F
(2) SMC block diagram
(a) Arbiter
(b) Memory manager
requests are arbitrated on a Round-Robin basis. Requests from the manager heve the
highest priority.
The Arbiter receives accesses from the SMC I/F and memory manager. Read/Write
Updates timing registers and controls commands issued to memory
Figure 3.10.17 is a SMC block diagram.
Manager
Memory
Arbiter
Figure 3.10.17 SMC block diagram
TENTATIVE
TMPA900CM- 239
Memory I/F
PAD I/F
SRAM memory I/F
Memory
Domain
EBI I/F
TMPA900CM
2009-10-14
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