BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 540

KIT STARTER TMPA900 USB JTAG

BMSKTOPASA900(DCE)

Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Datasheets

Specifications of BMSKTOPASA900(DCE)

Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
• Master Write transfer sequence
Note: UDC2AB will assert the int_mw_set_add interrupt when the packet is received normally from the USB host
(4) Master Write transfer
with the mw_enable bit of DMAC Setting register disabled.
operations will be as follows:
The operation of Master Write transfers are discussed here. Master Write
1. Set Master Write Start Address and Master Write End Address registers.
2. Set the bits associated to the Master Write operation of DMAC Setting
3. UDC2AB makes a Master Write transfer to the data in the endpoint
4. Since the int_mw_end_add interrupt will be asserted when the writing
register and set 1 to the mw_enable bit.
received from the USB host.
ended to reach the Master Write End Address (with no timeout processed),
you should make necessary arrangement with the software. UDC2 will
return to 1 after receiving the correct packet.
TENTATIVE
TMPA900CM- 539
TMPA900CM
2009-10-14

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