BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 392

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19. UART2LCR_H (UART2 Line control register)
[Description]
a. <SPS>
b. <WLEN>
c.
d. <STP2>
[31:8]
[7]
[6:5]
[4]
[3]
[2]
[1]
[0]
Bit
<FEN>
When bits 1, 2, and 7 of the UARTxLCR_H register are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and bit 2 is 0, the parity bit is transmitted
and checked as a 1. When this bit is cleared, the stick parity is disabled. Refer to Table
3.13.2 for the truth table of SPS, EPS, and PEN bits.
This bit indicates the number of data bits transmitted or received in a frame.
When this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode).
When this bit is cleared to 0, the FIFOs are disabled (character mode) and they become
1-byte deep holding registers.
When this bit is set to 1, two stop bits are transmitted at the end of a frame. The receive
logic does not check for the second stop bit being received.
−
SPS
WLEN
FEN
STP2
EPS
PEN
BRK
Symbol
Bit
−
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
TENTATIVE
TMPA900CM- 391
Undefined
0y0
0y00
0y0
0y0
0y0
0y0
0y0
Reset
Value
Read as undefined. Write as zero.
Stick parity select:
Refer to Table 3.13.2 for the truth table.
Word length:
0y00: 5 bits, 0y01: 6 bits
0y10: 7 bits, 0y11: 8 bits
FIFO control
0y1: FIFO mode
0y0: Character mode
Stop bit select
0y0: 1 stop bit
0y1: 2 stop bits
Even parity select (Refer to Table 3.13.2 for
the truth table.)
0y1: Even
0y0: Odd
Parity control (Refer to Table 3.13.2 for the
truth table.)
0y0: Disable
0y1: Enable
Send break
0y0: No effect
0y1: Send break
Address = (0xF200_4000) + (0x002C)
Description
TMPA900CM
2009-10-14