BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 206

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LCDDA
DMAC1
DMAC2
USB
output of LCDDA, USB, DMAC1, and
(Bus request from the bus matrix 3
3.10.3
CPU Inst (AHB0) bus request
LCDC (AHB2) bus requesst
CPU Data (AHB1) bus request
LCDC
CPU
Data
CPU
AHB
Inst
AHB3 bus request
Functions of MPMC0
Figure 3.10.1 is a simplified block diagram of MPMC0 circuits.
DMAC2)
(a)
Handling priority : ①→②→③→④→⑤
MPMC0
1. Bus matrix of AHB0, AHB1, AHB2 and AHB3 supports Round-Robin arbitation
Bus matrix
AHB3 interface M
scheme. The following diagram shows the priority of bus requests.
AHB0 interface M
AHB1 interface M
AHB2 interface M
Figure 3.10.1 MPMC0 Block Diagram
A dotted line is the point of handling end where bus is released.
①
③
④
②
TENTATIVE
AHB0
Handling
TMPA900CM- 205
Round-Robin
AHB1
Handling
S
S
S
S
Bus matrix
AHB2
Handling
⑤
M
M
AHB3
Handling
S
S
APB S
M
AHB to APB
bridge
APB S
AHB0
Handling
DMC
SMC
M
S
TMPA900CM
2009-10-14
SDR
1chip
SRAM/NOR
2chips