BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 57

Manufacturer Part Number

BMSKTOPASA900(DCE)

KIT STARTER TMPA900 USB JTAG

Manufacturer

Evaluation Board, Cable(s), Software and Documentation

For Use With/related Products

TMPA900CMXBG

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

from the XT1 and XT2 pins is defined as f

defined as clock f

clock obtained by dividing f

peripheral IPs connected to the APB bus, a clock obtained by dividing f

memory controller, and as a SRAM/NORF clock, f

by 2 can be selected (Please refer to MPMC section).

Clock frequency input from the X1 and X2 pins is defined as f

Also, two types of clock, for DRAM and for SRAM/NORF respectively, are input in the

(Signal name: PCLK)

for the CPU core. For peripheral IPs connected to the AHB bus, a

TMPA900CM- 56

by 2 is defined as f

, and the clock selected in SYSCR1<GEAR2:0> is

or a clock obtained by dividing f

(Signal name: HCLK). For

, clock frequency input

by 2 is defined