BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 681

KIT STARTER TMPA900 USB JTAG

BMSKTOPASA900(DCE)

Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Datasheets

Specifications of BMSKTOPASA900(DCE)

Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
g. <ACB>
h. <PCD_LO>
Note: There are limitations on the minimum values usable for the panel clock divider in the STN mode.
needs to be inverted periodically to prevent degradation in the LCD due to the
accumulation of DC electrical charge. The bias inversion period, which is specified in lines,
is the value set in this field incremented by one. Therefore, it can be set to 1 to 32 lines. This
field can be used only for STN displays.
The lower 5 bits of the value set for panel clock frequency division setting (10 bits)
• Single panel color mode: PCD = 1 (LCLCP = HCLK/3)
• Dual panel color mode: PCD = 4 (LCLCP = HCLK/6)
• Single panel monochrome 4-bit interface mode: PCD = 2 (LCLCP = HCLK/4)
• Dual panel monochrome 4-bit interface mode: PCD = 6 (LCLCP = HCLK/8)
• Single panel monochrome 8-bit interface mode: PCD = 6 (LCLCP = HCLK/8)
• Dual panel monochrome 8-bit interface mode: PCD = 14 (LCLCP = HCLK/16)
The ACB field specifies the bias inversion period. For STN displays, the bias polarity
TENTATIVE
TMPA900CM- 680
TMPA900CM
2009-10-14

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