BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 69

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.5.3
3.5.4
Examples of the PLL start and stop settings are as follows:
(1) Clock gear
System Clock Controller
PLL Clock Multiplier
other built-in I/Os (f
SYSCR1<GEAR2:0> to change the high speed clock gear to 1, 2, 4, or 8-speed (fc, fc/2, fc/4,
or fc/8) to reduce power consumption.
therefore, frequency of the CPU clock f
24 MHz oscillator is connected to the X1 and X2 pins, the frequency of f
MHz when reset operation is executed.
PLL, it is possible to lower the oscillator frequency and make the internal clock faster.
necessary to configure the SYSCR2, SYSCR3 and SYSCR4 registers when using the PLL.
operation is enabled, and the time required is called lock-up time.
time is approximately 164μs when f
Setting example – 1: PLL start
LOCKUP:
The system clock controller generates a clock to be supplied to the CPU core (f
Reset operation switches the mode to PLL-OFF, and <GEAR2:0> is initialized to 0y000;
The PLL outputs f
Since the PLL is initialized to the halt state when reset operation is executed, it is
As with an oscillator, this circuit requires time to stabilize the f
A 12-stage binary counter can be used to check the lock-up time. For example, lock-up
fc, fc/2, fc/4, or fc/8.
consumption.
By using the clock gear selection register SYSCR1<GEAR2:0>, the gear can be set to
Changing f
An example of clock gear switching is as follows:
;
(SYSCR1)
[Setting example]
SYSCR4
SYSCR3
SYSCR2
LDR
AND r0,r0,r1
LDR r1, = 0x01
CMP r0 ,r1
BNE LOCKUP
(SYSCR2)
r1, = 0x01
FCLK
PLL
HCLK
clock signals whose frequency is 6 or 8 times the f
by using the clock gear contributes to reduction of power
). With the f
←
←
→
←
TENTATIVE
TMPA900CM- 68
←
0x00000065
0x00000087
r0
0x00000002
OSCH
OSCH
FCLK
= 25 MHz.
0x0000_0011
or f
will be the same as f
PLL
; Set the constant of PLL x8
; Operation is activated with PLL x8
; <LUPFLAG> == 1?
;
; r0 ≠r1 ,
; <FCSEL> = 1 (change from 24 MHz to 192 MHz)
clock as an input, it is possible to use
jump to LOCKUP
; switch f
OSCH
. For example, when a
PLL
FCLK
clock signals after
OSCH
to 1/8.
FCLK
TMPA900CM
. By using the
2009-10-14
becomes 24
FCLK
) and