BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 202

• Manufacturer Part Number: BMSKTOPASA900(DCE)
• Description: KIT STARTER TMPA900 USB JTAG
• Manufacturer: Toshiba
• Series: TOPASr
• Type: MCUr

Specifications of BMSKTOPASA900(DCE)

• Contents: Evaluation Board, Cable(s), Software and Documentation
• For Use With/related Products: TMPA900CMXBG
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

According to the voltage of the connected external memory, set pin and register as follows.
related pin connections and the constant value setting register need be set.
Note: The PMCDRV register should be set during low-speed operation (PLL = OFF) after reset is released.
According to power voltage, adjust drive power of related ports. In the case of using SDRAM,
The following table shows the required setting.
Connect DMCCLKIN to DMCCLKP
Port drive power set register
PMCDRV<DRV_MEM1:0>
Bus width setting register
Bus width setting register
Note: The two memory controllers cannot be used by dynamically switching between them. The memory controller to
Note: The dmc_user_config_5 register should be set after reset is released and before SDRAM is initialized. This
[SDR SDRAM]
Note: The dmc_user_config_3 register should be set after reset is released and before SDRAM is initialized. This
[DDR SDRAM]
dmc_user_config_3
(Fix DMCCLKIN to GND)
dmc_user_config_5
This pin isn’t used.
Mode setting pin
be used must be fixed.
also applies after HOT_RESET by the PMC is released.
Pin treatment
also applies after HOT_RESET by the PMC is released.
pin treatment
DMCCLKIN
DMCCLKIN
SELDVCCM
0x00000000
0x00000001
0x00000058
0y11
0y01
0
1
Control pin of external memory except NAND Flash operate in the
DVCCM = 1.8 ± 0.1 V.
Control pin of external memory operate in the DVCCM = 3.3 ± 0.3 V.
control pin of external memory except NAND Flash operate in the
DVCCM = 1.8 ± 0.1 V
control pin of external memory operate in the DVCCM = 3.3 ± 0.3 V
16bit bus in SDR SDRAM (MPMC0)
32bit bus in SDR SDRAM (MPMC0)
16bit bus in DDR SDRAM (MPMC1)
16bit bus in DDR SDRAM (MPMC1)
TENTATIVE
(32bit bus DDR type SDRAM isn’t supported)
(32bit bus DDR type SDRAM isn’t supported)
TMPA900CM- 201
16/32 bit bus in SDR SDRAM (MPMC0)
Operation mode
Operation mode
Operation mode
Operation mode
Operation mode
Operation mode
TMPA900CM
2009-10-14