BMSKTOPASA900(DCE) Toshiba, BMSKTOPASA900(DCE) Datasheet - Page 8

KIT STARTER TMPA900 USB JTAG

BMSKTOPASA900(DCE)

Manufacturer Part Number
BMSKTOPASA900(DCE)
Description
KIT STARTER TMPA900 USB JTAG
Manufacturer
Toshiba
Series
TOPASr
Type
MCUr
Datasheets

Specifications of BMSKTOPASA900(DCE)

Contents
Evaluation Board, Cable(s), Software and Documentation
For Use With/related Products
TMPA900CMXBG
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Internal RAM0
Internal RAM2
8kB(Remap)
SD Host Controller
Interrupt Controller
NANDF Controller
16kB
CMOS image
Synchronous
LCD Data Process
Serial Port
Sensor I/F
Multi Layer Bus Matrix0
(Bus Master3)
(Bus Master4)
I2S I/F
(1ch)
(2ch)
Accelerator
(2ch)
(2ch)
Controller
Data Cache
LCD
16Kbyte
CPU Inst.
CPU Data.
Figure 1.1 TMPA900CM block diagram
DMA1
DMA2
Internal RAM1
USB Host 1.1
CPU Data
Boot ROM
Controller
LCDDA
LCDC
16kB
USB
8kB
LCDDA
CPU Inst.
LCDC
CPU Data
TENTATIVE
ARM926EJ
DMA1
DMA2
(Bus Master1&2)
TMPA900CM- 7
Bus Interface
CPU Data.
TM
CPU Data
DMA1
DMA2
-S
Controller
USB
SDR SDRAMC
Memory
SRAM
NORF
Bus Matrix3
Multi Layer
External Bus Interface
Controller
Instruction Cache
USB Device 2.0
DMA Controller
(Bus Master5&6)
16Kbyte
General purpose I/O
System Controller
Watch Dog Timer
Touch Screen I/F
Power Management
External Interruption
16Timer/PWM (6ch)
A/D converter (8ch)
PLL Clock Gear
Key board matrix
I2C I/F (2ch)
RTC/Melody
UART (3ch)
(Bus Master7)
OFD
Controller
DDR SDRAMC
Memory
NORF
SRAM
Bus Matrix2
Multi Layer
TMPA900CM
2009-10-14

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