HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 946

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 26
26.3.14 LCDC Vertical Sync Signal Register (LDVSYNR)
LDVSYNR specifies the vertical (scan direction and vertical direction) sync signal timing of the
LCD module.
Rev. 3.00 Jan. 18, 2008 Page 884 of 1458
REJ09B0033-0300
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
VSYNW3
VSYNW2
VSYNW1
VSYNW0

VSYNP10
VSYNP9
VSYNP8
VSYNP7
VSYNP6
VSYNP5
VSYNP4
VSYNP3
VSYNP2
VSYNP1
VSYNP0
LCD Controller (LCDC)
Initial Value
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Vertical Sync Signal Width
Set the width of the vertical sync signals (FLM and
Vsync) (unit: line).
Specify to the value of (the vertical sync signal
width) -1.
Example: For a vertical sync signal width of 1 line.
Reserved
This bit is always read as 0. The write value
should always be 0.
Vertical Sync Signal Output Position
Set the output position of the vertical sync signals
(FLM and Vsync) (unit: line).
Specify to the value of (the number of vertical sync
signal output position) -2.
DSTN should be set to an odd number value. It is
handled as (setting value+1)/2.
Example: For an 480-line LCD module and a
vertical retrace period of 0 lines (in other words,
VTLN=479 and the vertical sync signal is active for
the first line):
•
•
Single display
VSYNP = [(1-1)+VTLN]mod(VTLN+1)
Dual displays
VSYNP = [(1-1)×2+VTLN]mod(VTLN+1)
VSYNW = (1-1) = 0 = H'0
= [(1-1)+479]mod(479+1)
= 479mod480 = 479 =H'1DF
= [(1-1)×2+479]mod(479+1)
= 479mod480 = 479 =H'1DF