HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1283

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 36.2 H-UDI Commands
36.3.3
Shift register is a 32-bit register. The upper 16 bits are set in SDIR at Update-IR.
If shifted in, the shift-in value is shift-out after the value of the 32-bit shift register is shifted out.
36.3.4
SDBSR is a 434-bit shift register, located on the PAD, for controlling the input/output pins of this
LSI. The initial value is undefined. This register cannot be accessed by the CPU.
Using the EXTEST, SAMPLE/PRELOAD, CLAMP, and HIGHZ commands, a boundary scan
test supporting the JTAG standard can be carried out. Table 36.3 shows the correspondence
between this LSI's pins and boundary scan register bits.
TI7
0
0
0
0
0
0
1
1
1
TI6
0
0
0
1
1
1
0
1
1
Shift Register
Boundary Scan Register (SDBSR)
TI5
0
1
1
0
1
1
1
1
1
Other than the above
TI4
0
0
1
0
0
1

0
1
Bits 15 to 8
TI3









TI2









TI1









Section 36
Rev. 3.00
TI0









Jan. 18, 2008
Description
JTAG EXTEST
JTAG CLAMP
JTAG HIGHZ
JTAG SAMPLE/PRELOAD
H-UDI reset, negate
H-UDI reset, assert
H-UDI interrupt
JTAG IDCODE (Initial value)
JTAG BYPASS
Reserved
User Debugging Interface (H-UDI)
Page 1221 of 1458
REJ09B0033-0300